1. Field of the Invention
The present invention relates generally to an analog/digital converter, hereinafter referred to as "A/D converter", and more particularly to an A/D converter which converts analog voltage into digital value even if the lower-order bits of it are cut off.
2. Description of the Related Art
It is known in the art that single-chip microcomputers used in industry and homes is equipped with an A/D converter which converts analog voltage detected by various sensors into digital values. There are many kinds of sensors depending upon applications such as thermosensors, hygrometric sensors and barometric sensors.
In recent years, as microcomputer-based products are becoming more sophisticated and having multi-functions, the built-in A/D converters are required to have as high resolution as in the 10-bit order. However, all the output voltage of the sensors need not be converted into 10-bit digital values, but some sensors may be less precise. For example, in the case of an 8-bit CPU, an 8-bit data can be processed by an A/D converter at one time. In contrast, a 10-bit data must be divided into two parts, and taken in twice part by part, thereby taking a longer time for reading data in digit converted by the A/D converter. It is common practice to take in a data in the 10-bit order when high precision is required, and to take in an 8-bit data when less precision suffices. In this way, the conventional microcomputer-based appliances try to maintain efficiency by averaging the performance.
The way to obtain an 8-bit conversion by using a 10-bit A/D converter consists mainly of reading out exclusively the results of the high-order 8-bits conversion and ignoring the low-order two bits.
Referring to FIG. 1, which shows a construction of a general-purpose sequential comparison type A/D converter built in a microcomputer, an analog voltage AN to be converted is inputted to an input terminal of a comparator 1, and a comparison voltage outputted by the D/A convertor division 2 is input to the other input terminal of the comparator 1. The D/A converting division 2 includes a ladder resistor. The comparator 1 has a control terminal to which a control signal from a control circuit 3 is inputted. The results of comparison obtained by the comparator 1 are stored in a sequential approximation SA register 4 (hereinafter called "SA register 4"), and the conversion conducted by the SA register 4 is inputted to the D/A converting division 2. The SA register 4 is supplied with an address by an address decoder 5, and the conversion conducted by the SA register 4 is outputted to a data bus DB.
Now, referring to FIG. 2, which shows a schematic internal structure of the SA register 4, the SA register 4 is composed of 10 bits from MSB (most significant bit) b.sub.9 to LSB (least significant bit) b.sub.0, and includes a control division 4a for controlling its operation.
This type of A/D converter is operated as follows:
The control circuit 3 outputs a control signal to operate the A/D converter, thereby causing it to sets "1" at the MSB b.sub.9 in the SA register 4. Then the D/A convertor division 2 outputs a reference voltage (1/2) V.sub.ref. The comparator 1 compares the target analog voltage AN with the reference voltage (1/2) V.sub.ref. If the target analog voltage AN is smaller than the reference voltage, the MSB b.sub.9 is reset, and if it is larger than it, the MSB b.sub.9 is kept in its set state.
Then, "1" is set at the 2nd bit b.sub.8 in the higher order. If "1" is already set at the MSB, the D/A convertor division 2 outputs a reference voltage (3/4) V.sub.ref, and if not yet, a reference voltage (1/4) V.sub.ref is outputted. In this way, the comparator 1 conducts the 2nd comparison between the analog voltage AN and the reference voltage. If the comparison finds that the target analog voltage AN is smaller than the reference voltage, the 2nd-bit b.sub.8 is reset, and if the comparison finds that the target analog voltage is larger, the 2nd-bit b.sub.8 is kept in its set state. After the same procedures are repeated ten times, the target analog voltage is converted into 10-bit digital value. Then the address decoder 5 inputs an address in the SA register 4, and outputs the conversion thereof to the data bus DB.
In this ray, the SA register 4 selectively controls the taps of the ladder resistor circuits for the D/A convertor division 2 while the A/D conversion is proceeding. Finally the SA register 4 stores the results of the A/D conversion. The characteristics of the 10-bit A/D conversion are shown in FIG. 3 where the X-axis indicates the analog voltages of the low-order 4-bit in terms of digital values, and the Y-axis indicates the results of conversion of low-order 4-bit. In FIG. 3 the ladder-like fine line represents ideal A/D conversion characteristics obtainable when a 10-bit conversion is practiced. The ladder-like dotted lines represent the ideal conversion characteristics obtainable when an 8-bit conversion is practiced. The ladder-like thick line represents the 8-bit conversion obtainable when after a 10-bit conversion is finished, the low-order two bits are rounded off.
There are another type of A/D converters which are provided with at least one register especially for storing the results of conversion. However, the addition of such special registers does not give any favorable influence on the performance of the SA register 4 but it only increases the number of step for transmitting the results of conversion to the storage register.
As is evident from the foregoing, when the A/D conversion is practiced by a 10-bit converter and the low-order two bits are rounded off, the resulting characteristics is not satisfactory as indicated by the full lines in FIG. 3, which is different from the ideal one indicated in the dotted lines obtained by using an 8-bit A/D converter. This unavoidably involves an error by (3/8) LSB.